1. Field of the Invention
The present invention relates to a multiport memory device. In particular, the invention relates to a multiport memory device including plural input/output ports that operate at different clock frequencies.
2. Description of Related Art
Along with recent advancements of semiconductor technologies, smaller-size and larger-capacity memories that allow high-speed reading/writing operations have been developed. Further, a so-called multiport memory including plural input ports and output ports has been used for simultaneously reading/writing data of different addresses.
Hitherto, extensive studies have been made on the multiport memory. For example, Japanese Unexamined Patent Application Publication No. 8-279292 (hereinafter, referred to as “Related Art 1”) discloses a multiport memory where an address decoder is shared to reduce a circuit area.
The multiport memory described in Related Art 1 receives address data from two input ports that are switched by the address decoder. Then, a memory cell array operates at a doubled clock speed to process the data input from the two input ports. Thus, a single address decoder and a single memory cell array suffice for. In this way, an area for the multiport memory can be saved and a two-input system is realized.
The related multiport memory is described in brief. FIG. 4 is a block diagram showing the configuration of a conventional multiport memory device as described in Related Art 1, for example. A multiport memory device 2 of FIG. 4 includes a memory cell array 20, an input control circuit 21, an output control circuit 22, and a clock doubling circuit 23.
FIG. 5 is a timing chart showing a processing flow of the related multiport memory. An input clock of FIG. 5 is supplied to input data holding flip flops 210 and 211 in the input control circuit 21, and output data holding flip flops 222 and 223 in the output control circuit 22. This input clock is also supplied to the clock doubling circuit 23. The clock doubling circuit 23 doubles an input clock speed to generate a doubled clock as shown in FIG. 5. Then, the doubled clock is supplied to the memory cell array 20, an address decoder 212 in the input control circuit 21, and data holding latches 220 and 221 in the output control circuit 22.
Further, the clock doubling circuit 23 generates a selection signal based on the doubled clock, and supplies the generated selection signal to an input data selector 213 in the input control circuit 21 and an output data selector 224 in the output control circuit 22. Regarding the selection signal of FIG. 5, a portion A of FIG. 5 corresponds to a selection signal_A for selecting an input signal from an input port A, and a portion B corresponds to a selection signal_B for selecting an input signal from an input port B. These signals are output from the clock doubling circuit 23. The input data selector 213 receives the selection signals from the clock doubling circuit 23. The input data selector 213 selects one of the input data holding flip flop 210 and the input data holding flip flop 211 of the input control circuit 21 in response to the selection signal to receive input data (address data) from the input port A or the input port B. The input data selector 213 outputs the received address data to the address decoder 212.
Subsequently, a processing flow of the multiport memory device 2 described in Related Art 1 is explained in brief. The multiport memory device 2 receives address data from the two input ports, the input port A and the input port B. The input port A is connected with the input data holding flip flop 210 in the input control circuit 21. The input port B is connected with the input data holding flip flop 211.
The input data holding flip flop 210 and the input data holding flip flop 211 receive the same input clock to execute a data input processing from the input port A and the input port B in accordance with the input clock. Each input processing is executed at input-port timings of (0) to (2) of FIG. 5.
The input data selector 213 selects one of the input data holding flip flop 210 and the input data holding flip flop 211. As a result, the address data input from either the input port A or the input port B is supplied to the address decoder 212. That is, the input data selector 213 receives the selection signal from the clock doubling circuit 23 to select one of the input data holding flip flops 210 and 211 in accordance with the selection signal, and receive the address data held in the selected input data holding flip flop. Then, the selector sends the received data to the address decoder 212.
The address decoder 212 decodes the address data received from the input data selector 213 to read data stored at a corresponding address in the memory cell array 20. This processing is executed at a reading-processing timing of FIG. 5.
The memory cell array 20 outputs the thus-read data (hereinafter, referred to as “read data”) to the output data selector 224 in the output control circuit 22. The output data selector 224 selects one of the data holding latch 220 and the data holding latch 221 in accordance with the selection signal from the clock doubling circuit 23. Then, the selector sends the read data supplied from the memory cell array 20, to the selected data holding latch.
The data holding latch 220 outputs the read data to the output data holding flip flop 222 based on the doubled clock from the clock doubling circuit 23. Likewise, the data holding latch 221 outputs the read data to the output data holding flip flop 223 based on the doubled clock from the clock doubling circuit 23.
The output data holding flip flop 222 sends the received read data to the output port A. Similarly, the output data holding flip flop 223 sends the received read data to the output port B. The output data holding flip flop 222 and the output data holding flip flop 223 receive an input clock not subjected to a speed doubling processing, instead of the doubled clock, and then execute output processings in accordance with the input clock. The output processing is executed at output-port timings of (0) to (2) of FIG. 5.
In this way, in the multiport memory device of Related Art 1, the memory cell array operates at a doubled clock speed to process data input from the two input ports. Thus, a single address decoder and a single memory cell array suffice therefor. Accordingly, an area can be reduced, and a two-input system is realized.
However, in the multiport memory of Related Art 1, the same input clock is applied to the respective input data holding flip flops 210 and 211. Hence, the input clocks used for each port are limited to the same frequency, so the technique of Related Art 1 can be used only for an application where all ports operate with the same frequency.
Further, there have been proposed a dual-port memory where an internal clock speed is doubled to support two input and output ports (for example, Japanese Unexamined Patent Application Publication No. 7-84987) and a multiport memory where a higher-frequency one of a write clock and a read clock is selected and its clock speed is doubled (for example, Japanese Unexamined Patent Application Publication No. 2004-127440), but either memory has a problem in that the memory cannot operate unless clocks applied to input ports have the same clock frequency and phase.
Incidentally, in the case of using plural input ports, many users demand to operate the input ports at different clock frequencies. In such a case, albeit the same frequency, the input clocks may be out of phase. However, the related multiport memory has a problem of being unable to operate if the input clocks are different in clock frequency or phase.